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19-0611; Rev 7; 1/09
KIT ATION EVALU ABLE AVAIL
Direct-Conversion TV Tuner
General Description
The MAX3580 fully integrated, direct-conversion TV tuner is designed for Digital Video Broadcasting-Terrestrial (DVB-T) applications. The integrated tuner covers a 170MHz to 230MHz input frequency range for the VHF-III band and 470MHz to 878MHz for the UHF band. The MAX3580 direct-conversion tuner integrates an RF input switch and a multiband tracking filter, allowing low-power tuner-on-board applications without the cost and power-dissipation issues of dual-conversion tuner solutions. The zero-IF architecture eliminates the need for SAW filters by providing baseband I and Q outputs directly to the demodulator. In addition, DC-offset cancellation is implemented on-chip using a mixed-signal architecture to improve the second-order distortion performance and the dynamic range of the downstream digitizer and demodulator. The MAX3580 features dynamic gain control of more than 76dB and a typical midband noise figure of 4.7dB referred to the LNA input. The VCO architecture optimizes both in-band and wideband phase noise for OFDM applications where sensitivity to both 1kHz phase noise and wideband phase noise related to strong adjacents can be a problem. The MAX3580 communicates using a 2-wire serial bus. The device operates from a typical +3.3V power supply and dissipates 650mW. The MAX3580 is available in a small 32-pin thin QFN package (5mm x 5mm) with an exposed paddle.
Features
650mW Power Dissipation (at VCC = +3.3V) I and Q Baseband Outputs Eliminate All IF-SAW Filters Integrated RF Tracking Filters Tunable Baseband Lowpass Filters Full-Band VHF-III and UHF Tuning +38dB Digital ACPR, +47dB Analog ACPR Low Noise Figure: 4.7dB (typ) Frac-N Synthesizer for -90dBc/Hz Close-In Phase Noise +3.1V to +3.5V Supply Voltage Range Ultra-Small, 5mm x 5mm Thin QFN Package
MAX3580
Pin Configuration/ Functional Diagram
TOP VIEW
VCC_XTAL REF_BUFF VCC_SYN GND_PLL GND_CP 25 CHARGE PUMP MAX3580 SCL 2 SERIAL INTERFACE, CONTROL, AND SYNTHESIZER 23 LDO MUX
Applications
Digital Televisions Digital Terrestrial Set-Tops Laptop Televisions Automotive Televisions USB Peripherals
RFIN 4
XB
XE
32
31
30
29
28
27
26
+
SDA 1 24 CP
RFIN2 3
LO
22 GND_TUNE
21 VTUNE
Ordering Information
PART MAX3580ETJ+ MAX3580ETJ+T TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 32 TQFN-EP* 32 TQFN-EP*
ADDR2 5
20 VCC_VCO
GND_LNA 6 TRACKING FILTER VCC_RF 7 0 90 LO
19 BB_AGC
18 BBI+
RF_AGC
OVLD_DET
BBQ-
________________________________________________________________ Maxim Integrated Products
VCC_BB
BBQ+
IND1
IND2
N.C.
*EP = Exposed paddle. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape-and-reel package.
LEXT 8
17 BBI-
9
10
11
12
13
14
15
16
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Direct-Conversion TV Tuner MAX3580
ABSOLUTE MAXIMUM RATINGS
VCC_ _ to GND......................................................-0.3V to +3.6V SDA, SCL, ADDR2, MUX, REF_BUFF, BB_AGC, RF_AGC to GND ................................-0.3V to +3.6V All Other Pins to GND ..............................-0.3V to (+VCC + 0.3V) RF Input Power ...............................................................+10dBm Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +165C Continuous Power Dissipation (TA = +70C) (derate 21.3mW/C above +70C) ..............................1702mW Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX3580 EV kit, VCC = +3.1V to +3.5V, VGND = 0, VBB_AGC = VRF_AGC = +2.85V, RF input terminated into a 75 load, BBI_ and BBQ_ are open, no input signal, VCO active, registers set according to the specified default register conditions, unless otherwise specified. Typical values are at VCC = +3.3V, TA =+25C, unless otherwise specified.) (Note 1)
PARAMETER Supply Voltage Supply Current RF_AGC AND BB_AGC Input Bias Current RF and Baseband AGC Control Voltage IAGC VAGC VAGC at +0.5V and +2.85V Maximum gain Minimum gain -50 2.85 0.5 0.3 x VCC 0.7 x VCC 0.05 x VCC -10 VOL VOH Sink current = 0.3mA Source current = 0.3mA VCC 0.5 +10 0.4 +50 A V SYMBOL VCC ICC Active Shutdown mode CONDITIONS MIN 3.1 197 <100 TYP MAX 3.5 225 UNITS V mA A
SUPPLY VOLTAGE AND CURRENT
SERIAL INTERFACE AND MUX OUTPUT (SCL, SDA, MUX) Input Logic-Level Low Input Logic-Level High Input Hysteresis SDA, SCL Input Current Output Logic-Level Low Output Logic-Level High VIL VIH V V V A V V
2
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Direct-Conversion TV Tuner
AC ELECTRICAL CHARACTERISTICS
(MAX3580 EV kit, VCC = +3.1V to +3.5V, VGND = 0. VRF_AGC = VBB_AGC = +2.85V, RF input terminated into a 75 load, BBI_ and BBQ_ loaded by RL greater than 2k and CL less than 10pF, VCO active, registers are set according to the recommended default register conditions, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Operating Frequency Range Overall Voltage Gain (Note 2) RF Gain Flatness Input Return Loss Noise Figure (DSB) (Notes 3, 4) NF SYMBOL fRF CONDITIONS Gain specification met across this frequency band RF_AGC = BB_AGC = +2.85V RF_AGC = BB_AGC = +0.5V Within each VHF-III and UHF band (Note 10) Worst case across band selected, 75 system 230MHz 470MHz 858MHz Input 2nd-Order Intercept Point IIP2 Broadband (Notes 4, 5) Broadband, RF_AGC adjusted for 49dB of gain Broadband (Notes 4, 6) Broadband, RF_AGC adjusted for 49dB of gain Input 3rd-Order Intercept Point IIP3 Narrowband (Notes 4, 7) Narrowband, RF_AGC adjusted for 49dB of gain (Note 7) PDESIRED = -78dBm and converted to 3.75MHz, PTONE 10MHz higher (Note 4) RF_AGC adjusted for 49dB of gain, PDESIRED = -55dBm LO Harmonic Reception RF Channel Flatness Isolation Quadrature Accuracy RF input range of 170MHz to 960MHz (Note 8) RF input range of 960MHz to 1400MHz 8MHz RF channel at baseband, tested at 169MHz and 469MHz DC to 30MHz, RF input to baseband output, relative to desired channel I/Q phase error at 1MHz I/Q amplitude error at 1MHz 50MHz to 470MHz Spurious at the RF Input (Note 3) 470MHz to 878MHz 878MHz to 1732MHz At 1kHz to 10kHz (Note 3) Phase Noise (Single-Sideband, Closed Loop) N At 100kHz (Note 3) At 1MHz -80 -94 -3 -1.5 -50 -50 < -50 -90 -107 -130 dBc/Hz -1 > 60 +3 +1.5 -20 -35 -20 dBmV -3 7 5.4 4.7 6.5 15 > 26 > -4 > 12 -6 +16 -22 dBm +1 > -60 > -40 +1 dBc dB dBc Degrees dB dBm dBm dB MIN 170 470 74 26 +3 TYP MAX 230 878 UNITS MHz dB dB dB
MAX3580
RF 1dB Desense
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3
Direct-Conversion TV Tuner MAX3580
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX3580 EV kit, VCC = +3.1V to +3.5V, VGND = 0. VRF_AGC = VBB_AGC = +2.85V, RF input terminated into a 75 load, BBI_ and BBQ_ loaded by RL greater than 2k and CL less than 10pF, VCO active, registers are set according to the recommended default register conditions, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER REFERENCE OSCILLATOR Frequency Input Impedance Voltage Gain Output Impedance Buffered Output DIVIDERS RF N Divider Ratio RF R Divider Ratio Fractional-N Resolution LO PHASE DETECTOR AND CHARGE PUMP Phase-Detector Frequency Charge-Pump Current Charge-Pump Tri-State Current Charge-Pump Compliance Range LOCAL OSCILLATOR Tuning Frequency Range VCO Dividers BASEBAND STAGE Nominal Output Voltage 1dB Output Compression Point Output Impedance Passband AGC Range Passband Cutoff Attenuation Passband Differential Gain Error Passband Group Delay Group Delay Mismatch P1dB (Note 2) Differential voltage at 3MHz Differential BB_AGC = 0.5V to 2.85V At 3.8MHz (UHF Mode); at 3.325MHz (VHF Mode) 2MHz to 3.8MHz, I channel vs. Q channel (UHF mode) From DC to 3.8MHz over any 1.1kHz band (UHF mode) From 0.1MHz to 3.8MHz, I channel vs. Q channel (UHF mode) (Note 9) -0.45 5 <2 30 1.6 1 2 60 50 2 5 +0.45 VP-P VP-P dB dB dB ns ns fOSC Tank Frequency 2160 4 4400 16 MHz -- Charge-pump positive to negative current matching of 5% ICP Gain = 0 Gain = 1 -10 0.4 4 600 1200 +10 VCC 0.4 27 MHz A A V (Notes 12, 13) VHF band operation requires R divider = 2 12 1 20 251 2 -- -- Bits ZOUT 10k || 10pF load 0.7 fREF ZIN 4 10 30 15 27 MHz k V/V VP-P SYMBOL CONDITIONS MIN TYP MAX UNITS
SIGMA-DELTA FRACTIONAL-N SYNTHESIZER
4
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Direct-Conversion TV Tuner
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX3580 EV kit, VCC = +3.1V to +3.5V, VGND = 0. VRF_AGC = VBB_AGC = +2.85V, RF input terminated into a 75 load, BBI_ and BBQ_ loaded by RL greater than 2k and CL less than 10pF, VCO active, registers are set according to the recommended default register conditions, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS At 5.25MHz (UHF mode) At 4.75MHz (VHF mode) Rejection Ratio At 13.25MHz (UHF mode) At 11.75MHz (VHF mode) At > 16.2MHz DC Output Voltage Output DC Offset Baseband Highpass Cutoff AGC Gain Slope Ratio of Passband to Stopband Noise 2-WIRE INTERFACE Clock Rate 400 kHz VCM Common mode (Note 11) BB_AGC = 2.85V Programmable BB_AGC = 0.5V to 2.85V BB_AGC = 2.85V, 10kHz to 3.8MHz vs. 16.2MHz to 23.8MHz 14 15 -70 20 to 200 35 MIN 23 23 63 62 84 0.485 x VCC +70 VDC mV Hz dB/V dB dB TYP MAX UNITS
MAX3580
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13:
Part is tested and guaranteed only at hot temperature. The specified overall voltage gain is suitable to amplify -93dBm to -20dBm to 1VP-P at the baseband output. Guaranteed by design characterization over the specified operating conditions. Not production tested. BB_AGC adjusted for gain = 72dB with RF_AGC at 2.85V. Two tones at a) 230MHz and 431MHz with IM measured at 201MHz and b) 230MHz and 701MHz with IM measured at 471MHz. Two tones at 499MHz and 689MHz with IM measured at 879MHz. IM3 measured with two tones within the adjacent channel at a) 205.75MHz and 210.5MHz with IM measured at 201MHz and b) 475.25MHz and 479.5MHz with IM measured at 471MHz. Measured at RF = 171MHz with harmonics at 511MHz (3rd harmonic) and 851MHz (5th harmonic). Delay of 2ns equal 2.74 phase error. UHF rolloff of 4dB in addition to gain flatness specification. Production tested at VCC = +3.5V to limits of 1.7V -0.12/+0.1V. Operation in the VHF band requires the R-divider = 2. Operation of the N-divider at values below 12 is not tested or guaranteed.
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5
Direct-Conversion TV Tuner MAX3580
Performance to Standards
The following is selected overall performance data for the MAX3580 + digital demodulator. Table 1 shows the typical overall performance as measured using the MAX3580 and one current production DVB-T demodulator. This reference design is available in NIM card form factor upon request. MBRAI refers to standard MBRAI 04-102 IEC 62002-1 available from www.ansi.org. NorDig refers to standard Unified 1.0.2 available from www.nordig.org. Modulation of wanted and interfering channel(s) is 8k mode, 16 QAM, C/R = 3/4, GI = 1/4, sensitivity or immunity Reference Bit Error Rate is 2 x 10e-4, unless stated otherwise.
Table 1. Selected Typical MBRAI and NorDig Performance
TEST SCENARIO MBRAI S2 MBRAI S2 MBRAI L3 NorDig 16 QAM 2/3 NorDig QPSK 1/2 NorDig 64 QAM 7/8 COMMENTS Immunity/ACPR for N 1 adjacent ch. Immunity/ACPR N 2 alternate ch. Linearity/crossmod. with N+2 and N+4 ch. Sensitivity at channel 21 (470 MHz) Sensitivity at channel 42 (642 MHz) Sensitivity at channel 59 (778 MHz) SPEC MINIMUM 29dB 40dB 40dB -84.1dBm -92.1dBm -74.7dBm MAX3580 TYPICAL 40dB 43dB 47dB -85.1dBm -94.8dBm -76dBm
6
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Direct-Conversion TV Tuner
Typical Operating Characteristics
(MAX3580 Evaluation Kit, typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
VOLTAGE GAIN vs. RF_AGC CONTROL VOLTAGE
MAX3580 toc02
MAX3580
VHF-III BAND VOLTAGE GAIN vs. FREQUENCY
MAX3580 toc01
UHF BAND VOLTAGE GAIN vs. FREQUENCY
110 110 100 90 80 TA = 0C GAIN (dB) TA = +25C 90 70 60 50 40 TA = +85C TA = +55C 30 20
BB_AGC = 2.85V TA = -40C
100 TA = +25C GAIN (dB) 90 TA = 0C GAIN (dB)
100
TA = +25C, +55C TA = +85C
80
TA = +85C
TA = +55C
80
70 150 160 170 180 190 200 210 220 230 240 250 FREQUENCY (MHz)
70 450 500 550 600 650 700 750 800 850 900 FREQUENCY (MHz)
10 0 0.5 1.0 1.5 2.0 2.5 3.0 RF_AGC CONTROL VOLTAGE (V)
PHASE NOISE vs. OFFSET FREQUENCY
MAX3580 toc04
NOISE FIGURE vs. VHF FREQUENCY
MAX3580 toc05
NOISE FIGURE vs. UHF FREQUENCY
MAX3580 toc06
-50 -60 PHASE NOISE (dBm/Hz) -70 620MHz -80 -90 -100 -110 -120 0.1 1 10 100 OFFSET FREQUENCY (kHz) 220MHz
20
20
15 NOISE FIGURE (dB) TA = +85C TA = +55C 10 NOISE FIGURE (dB)
15 TA = +25C TA = +85C TA = +55C TA = -40C
10
5 TA = -40C TA = +25C 1000 0 150
5
0 175 200 225 FREQUENCY (MHz) 250 450 500 550 600 650 700 750 800 850 900 FREQUENCY (MHz)
VHF MODE NOISE FIGURE vs. VOLTAGE GAIN
MAX3580 toc07
30 25 NOISE FIGURE (dB) 20 15 10 5 0 60 65 70 75 80 85 TA = -40C TA = +25C, +55C fRF = 220MHz BB_AGC = 2.85V TA = +85C
90
VOLTAGE GAIN (dB)
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MAX3580 toc03
110
7
Direct-Conversion TV Tuner MAX3580
Typical Operating Characteristics (continued)
(MAX3580 Evaluation Kit, typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
UHF MODE NOISE FIGURE vs. VOLTAGE GAIN
MAX3580 toc08
VOLTAGE GAIN vs. BB_AGC CONTROL VOLTAGE
100 90 80 GAIN (dB) 70 60 50 40 30 TA = +85C TA = +25C, +55C RF_AGC = 2.85V TA = -40C
MAX3580 toc09
BASEBAND FILTER REJECTION RATIO
-10 -20 REJECTION RATIO (dB) -30 -40 -50 -60 -70 -80 -90 -100 NOISE LIMITED 0 5 10 15 FREQUENCY (MHz) 20 VHF INPUT UHF INPUT
MAX3580 toc10
30 25 NOISE FIGURE (dB) 20 15 10 5 0 60 65 70 75 80 85 TA = +25C TA = -40C TA = +85C TA = +55C
110
0
fRF = 620MHz BB_AGC = 2.85V 90
20 10 0 0.5 1.0 1.5 2.0 2.5 3.0
VOLTAGE GAIN (dB)
BB_AGC CONTROL VOLTAGE (V)
NORMALIZED BASEBAND FREQUENCY RESPONSE
MAX3580 toc11
NORMALIZED BASEBAND FREQUENCY RESPONSE
MAX3580 toc12
NORMALIZED BASEBAND FREQUENCY RESPONSE
0 -5 -10 -15 -20 -25 -30 -35 -40 TA = 0C TA = +85C BB_BW<3:0> = "1011" 8MHz CHANNEL MODE
MAX3580 toc13
5 0 -5 -10 GAIN (dB) -15 -20 -25 -30 -35 -40 -45 -50 0 1 2 3 4 5 FREQUENCY (MHz) BB_BW<3:0> = "1011" 8MHz CHANNEL MODE TA = 0C TA = +25C TA = +85C
5 0 -5 -10 GAIN (dB) -15 -20 -25 -30 -35 -40 -45 -50 0 1 2 3 4 5 FREQUENCY (MHz) BB_BW<3:0> = "1001" 7MHz CHANNEL MODE TA = 0C TA = +25C TA = +85C
5
GAIN (dB)
-45 -50 0 5 10
TA = +25C 15 20 25
FREQUENCY (Hz)
NORMALIZED BASEBAND FREQUENCY RESPONSE
0 -5 -10 GAIN (dB) -15 -20 -25 -30 -35 -40 -45 0 5 10 15 FREQUENCY (MHz) 20 25 TA = +25C TA = +85C TA = 0C BB_BW <3:0> = "1001" 7MHz CHANNEL MODE
MAX3580 toc14
5
8
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Direct-Conversion TV Tuner
Typical Operating Characteristics (continued)
(MAX3580 Evaluation Kit, typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
MAX3580
STOPBAND NOISE vs. FREQUENCY
MAX3580 tpc15
VHF MODE NOISE FIGURE vs. BB_AGC VOLTAGE
MAX3580 toc16
UHF MODE NOISE FIGURE vs. BB_AGC VOLTAGE
620MHz RF_AGC = 2.85V
MAX3580 toc17
30 25 NOISE FIGURE (dB) 20 15 TA = +85C 10 5 0 220MHz RF_AGC = 2.85V
30 25 NOISE FIGURE (dB) 20 15 10 5 TA = +55C TA = +85C
-45 STOPBAND NOISE (dBm)
-55 BB_BW <3:0> = "1011" 8MHz CHANNEL MODE -65 BB_BW <3:0> = "1001" 7MHz CHANNEL MODE -75 0 10 20 30 40 50 FREQUENCY (MHz)
TA = +55C
TA = -40C 0 0.5 1.0
TA = +25C 0 1.5 2.0 2.5 3.0 0
TA = -40C TA = +25C 0.5 1.0 1.5 2.0 2.5 3.0
BB_AGC VOLTAGE (V)
BB_AGC VOLTAGE (V)
RF PORT-TO-PORT ISOLATION
MAX3580 toc18
RF INPUT RETURN LOSS vs. UHF FREQUENCY
Zo = 75
MAX3580 toc19
40 35 30
0
RETURN LOSS (dB)
GAIN (dB)
25 20 15 10 5 0 RFIN TO RFIN2
-5
RFIN2 TO RFIN
-10
-15 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) 450 525 600 675 750 825 900 UHF FREQUENCY (MHz)
RF INPUT RETURN LOSS vs. VHF FREQUENCY
Zo = 75
MAX3580 toc20
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX3580 toc21
0
200 TA = +25C TA = 0C 195 ICC (mA) TA = -40C
-5 RETURN LOSS (dB)
-10
190 -15 TA = +55C -20 150 175 200 225 250 VHF FREQUENCY (MHz) 185 3.0 3.1 3.2 3.3 VCC (V)
TA = +85C
3.4
3.5
3.6
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9
Direct-Conversion TV Tuner MAX3580
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 -- NAME SDA SCL RFIN2 RFIN ADDR2 GND_LNA VCC_RF LEXT RF_AGC IND1 IND2 N.C. OVLD_DET VCC_BB BBQBBQ+ BBIBBI+ BB_AGC VCC_VCO VTUNE GND_TUNE LDO CP GND_CP VCC_SYN GND_PLL MUX REF_BUFF VCC_XTAL XB XE EP FUNCTION Serial-Data Input Line. Requires a pullup resistor to VCC. Serial-Clock Input. Requires a pullup resistor to VCC. Second RF Input First RF Input Address Line. Sets the 3rd LSB of the device address. Connect to ground to set for "0" or VCC to set for "1." Not Internally Connected. Connect to ground. DC Supply for RF LNA. Connect as close as possible a 100pF capacitor from this pin to GND. External Bias Inductor. Connect to VCC with a 270nH inductor. Gain Control Input for RF VGA. VHF Inductor Pin 1. Keep traces to inductor as short as possible. VHF Inductor Pin 2. Keep traces to inductor as short as possible. No Connection Overload Detector Output. No connection required to this pin. DC Supply for Baseband Filter. Connect as close as possible a 10nF capacitor from this pin to ground. Quadrature Inverted Baseband Output Quadrature Noninverted Baseband Output In-Phase, Inverted Baseband Output In-Phase, Noninverted Baseband Output Gain Control Input for Baseband VGAs DC Supply for the VCO. Connect as close as possible a 100pF capacitor from this pin to ground. VCO Tuning Voltage Input. Connect the PLL loop filter output directly to this pin. Ground Reference for the Tuning Voltage. Connect to ground of the loop filter. VCO LDO Output. Connect a 0.1F capacitor to ground. Charge-Pump Output. Connect the charge-pump output to the PLL loop filter input. Ground for the Charge Pump DC Supply for Synthesizer and Serial-Interface Control. Connect as close as possible a 10nF capacitor from this pin to ground. Ground for the PLL Multiplex Output Line. Can be used as a PLL lock-detector output. Buffered Output of Reference Oscillator DC Supply for Reference Oscillator. Connect as close as possible a 10nF capacitor from this pin to ground. Reference Input. Connect to a parallel resonant mode XTAL through a load-matching capacitor, or can also be used as a reference clock input pin. Reference Oscillator Feedback. Connect to a capacitive divider when used in self-oscillating mode. Exposed Paddle. Internally connected to ground. Solder EP to the board's ground plane to achieve the lowest possible impedance path and optimum RF performance.
10
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Direct-Conversion TV Tuner
Typical Application Circuit
VCC REF_BUFF VCC
MAX3580
VCC_XTAL
VCC_SYN
GND_PLL
32
31
30
29
28
27
26
GND_CP 25
MUX
XB
XE
SDA
1 MAX3580
CHARGE PUMP
24
CP
SCL
2
23
LDO
RFIN2
3
SERIAL INTERFACE, CONTROL, AND SYNTHESIZER
LO
22
GND_TUNE
RFIN
4
21
VTUNE
ADDR2
5
20
VCC_VCO
VCC
GND_LNA
6 TRACKING FILTER 7 0 90 LO
19
BB_AGC
VCC
VCC_RF
18
BBI+ I CHANNEL
VCC
LEXT
8
17
BBI-
9 RF_AGC
10 IND1
11 IND2
12 N.C.
13 OVLD_DET
14 VCC_BB
15 BBQ-
16 BBQ+
VCC
Q CHANNEL
RF_AGC
MAX3580
BB_AGC 1nF 10k 1k 39k Rohm 2SA1037AK 1F 100nF 1k DEMODULATOR PWM RF_AGC 3.3V
Figure 1. Single-Loop AGC Schematic
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Direct-Conversion TV Tuner MAX3580
Detailed Description
Programmable Registers
The MAX3580 includes thirteen write/read registers and three read-only registers. See Table 2 for register configuration and the Register Description section. The register configuration of Table 2 shows each bit name and the bit usage information for all registers. "U" labeled under each bit name indicates that the bit value is user defined to meet specific application requirements. A "0" or "1" indicates that the bit must be set to the defined "0" or "1" value for proper operation. Operation is not tested or guaranteed if these bits are programmed to other values and is only for factory/bench evaluation. For field use, always program to the defined operational state. Note that all registers must be written after and no earlier than 100s after device power-up. Note: To correctly tune the VCO during a channel change, first write to Register 0x05, continuing through Register 0x06 to Register 0x12, and then write to Register 0x00 through Register 0x04.
Table 2. Register Configuration
8-BIT DATA REGISTER ADDRESS D7 N7 U MP 0 F15 U F7 U TFS<7> U VCO_DIV1 U RDIV U CP_TST2 0 X 0 VCO1 U BB_BW3 U BB_BIA 0 DC_DAC7 0 X 0 TFD<7> 0 X 0 TFR<7> POR VCO1A D6 N6 U LI1 0 F14 U F6 U TFS<6> U VCO_DIV0 U ICP U CP_TST1 0 SHDN_BG U VCO0 U BB_BW2 U DC_DAC8 0 DC_DAC6 0 FUSE_TH 0 TFD<6> 0 X 0 TFR<6> VASA VCO0A D5 N5 U LI0 0 F13 U F5 U TFS<5> U RFS U CPS U CP_TST0 0 SHDN_PD 1 BS2 U BB_BW1 U DC_MO1 1 DC_DAC5 0 X 0 TFD<5> 0 X 0 TFR<5> VASE BS2A D4 N4 U INT U F12 U F4 U TFS<4> U TF_BS U ADLY1 0 X 0 SHDN_REF U BS1 U BB_BW0 U DC_MO0 1 DC_DAC4 0 WR 0 TFD<4> 0 X 0 TFR<4> LD BS1A D3 N3 U F19 U F11 U F3 U TFS<3> U TFP<3> U ADLY0 1 TURBO 1 SHDN_SYN U BS0 U X 0 DC_SP1 1 DC_DAC3 0 TFA<3> U TFD<3> 0 MX_HR<3> 0 TFR<3> DC_LO BS0A D2 N2 U F18 U F10 U F2 U TFS<2> U TFP<2> U LF_DIV2 U LD_MUX2 U SHDN_MX U VAS 1 PD_TH2 U DC_SP0 0 DC_DAC2 0 TFA<2> U TFD<2> 0 MX_HR<2> 0 TFR<2> DC_HI ADC2 D1 N1 U F17 U F9 U F1 U TFS<1> U TFP<1> U LF_DIV1 U LD_MUX1 U SHDN_BB U ADL 0 PD_TH1 U DC_TH1 0 DC_DAC1 0 TFA<1> U TFD<1> 0 MX_HR<1> 0 TFR<1> GKT ADC1 D0 N0 U F16 U F8 U F0 U TFS<0> U TFP<0> U LF_DIV0 U LD_MUX0 U SHDN_RF U ADE 0 PD+TH0 U DC_TH0 0 DC_DAC0 0 TFA<0> U TFD<0> 0 MX_HR<0> 0 TFR<0> PD_OVLD ADC0 REGISTER SETTINGS OPERATION DEFINED -- -- -- -- -- -- -- -- -- -- -- h38 h00 -- h00 h00 DEFAULT SETTINGS (POR) H17 h18 h00 h00 hDB h7C h0A h08 h00 hC0 h87 h40 h00 h00 h00 h00 N/A N/A N/A REGISTER NAME
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12
N-Divider Integer N-Divider Frac2 N-Divider Frac1 N-Divider Frac0 Tracking Filter Series Caps Tracking Filter Parallel Cap PLL Configuration Test Functions Shutdown Control VCO Control Baseband Control DC Offset Control DC Offset DAC ROM Table Address ROM Table Fuse Data Mixer Harmonic Rejection ROM Table Data Read Back Chip Status Read Back Autotuner Read Back
N/A N/A N/A
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Direct-Conversion TV Tuner
Register Descriptions
N-Divider Integer (Register Address 0x00) N<7:0>: VCO Integer-N Divider Ratio N-Divider Frac2 (Register Address 0x01) MP: Minimum CP Pulse Width. Always set to 0 (factory use only). LI1, LI0; CP Linearity Control. Always set to 00 (factory use only). INT: Integer Mode ON/OFF. Set to 0 for normal operation. F<19:16>: MSB of Main Divider Fractional Divide Ratio N-Divider Frac1, Frac0 (Register Address 0x02, 0x03) F<15:0> 16 LSB of Main Divider Fractional Divide Ratio Tracking Filter Series Capacitor (Register Address 0x04) TFS<7:4>: Tracking Filter Parallel Capacitor. TFS<3:0>: Tracking Filter Series Capacitor. See the RF tracking filter description in the Applications Information section. Tracking Filter Parallel Capacitor and VCO Control (Register Address 0x05) VCO_DIV1, VCO_DIV0: VCO Post Divider 00 = Divide by 4 use for RF frequencies of 540 to 868 MHz 01 = Divide by 8 use for RF frequencies of 470 to 550 MHz 10 = Divide by 16 use for RF frequencies of 170 to 230 MHz 11 = Divide by 32 is not used RFS: RF Input Select 0 = RFIN2 selected 1 = RFIN selected TF_BS: Tracking Filter Band Select 1 = VHF band 0 = UHF band TFP<4:0>: Tracking Filter Shunt Capacitor See the RF tracking filter description in the Applications Information section. PLL Configuration (Register Address 0x06) LF_DIV2, LF_DIV1, LF_DIV0: Prescaler for Internal Low Frequency Clocks
000 - 110 = Divided by 8 to 14 for REF crystal frequencies of 15MHz to 28MHz 111 = Divide by 2 for REF crystal frequencies of 4MHz ADLY1, ADLY0: VCO Autotuner Delay Selection CPS: Charge-Pump Current Mode 0 = Controlled by ICP bit 1 = Controlled by VCO autotuner ICP: Charge-Pump Current 0 = 600A 1 = 1200A RDIV: PLL Reference Divider Ratio 0 = Divide by 1 1 = Divide by 2
MAX3580
Test Functions (Register Address 0x07) CP_TST<2:0>: Charge-Pump Test Modes 000 = Normal operation
100 = Low impedance* 101 = Source 110 = Sink 111 = High impedance LD_MUX: Lock-Detector Mode 000 = Normal operation: high = PLL locked, low = unlocked 001 = Monitor N-divider output, post-divided by 2 010 = Monitor R-divider output* 011 = Modulator test vector output (factory use only) 1XX = Bias current trim (factory use only)
*Not production tested.
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Direct-Conversion TV Tuner MAX3580
Shutdown Control (Register Address 0x08) SHDN_BG: Main Bandgap 0 = Enabled 1 = Disabled
The main bandgap can and will be shut down once all other blocks are shut down (i.e., all bits in this shutdown register and bits VCO_ in the VCO Control Register and bits DC_MO_ in the DC Offset Control Register are shut down). SHDN_PD: Baseband Power Detector For factory use only. Set to 1 at all times. SHDN_RF: RF LNA/VGA: 0 = Enabled 1 = Disabled SHDN_MIX: I/Q Mixer and LO Drivers 0 = Enabled 1 = Disabled SHDN_BB: Baseband Filters and VGA 0 = Enabled 1 = Disabled SHDN_SYN: Fractional PLL 0 = Enabled 1 = Disabled SHDN_REF: Controls the Crystal Oscillator Buffered Output 0 = Enabled 1 = Disabled The XTAL oscillator activation results from the SHDN_SYN, SHDN_REF bits: If either one is on, the XTAL oscillator runs. The XTAL oscillator is shut down only if both bits are off. VAS: VCO Band Autoselect 0 = VCO band select controlled by bits VCO<1:0> 1 = Controlled by autotuner ADL: VCO ADC Latch Enable Bit 1 = Latches ADC value 0 = Default ADE: Enable VCO Tune Voltage DAC Read 1 = Enables ADC read 0 = Default
Baseband Control (Register Address 0x0A) PD_TH<2:0>: Detection Threshold for Baseband Power Detector BB_BW<3:0>: Baseband Filter Bandwidth. Optimum values for 7MHz and 8MHz wide RF channels can be taken from the ROM table. DC Offset Control (Register Address 0x0B) DC_TH<1:0>: DC Offset Correction Thresholds. Keeps output within: 00 = Output within 0.55V of balanced state
11 = Output within 0.75V of balanced state DC_SP<1:0>: DC Offset Correction Speed (or Highpass Corner Frequency). 11 = Fast (~500Hz) 01 = Slow (~20Hz) 00 = Off/hold DAC values DC_MO<1:0>: Mode of Operation 00 = Off 10/01 = Sets I/Q channel DACs direct from register 11 = Normal operation DC_DAC<8>: MSB for DC Offset DAC BB_BIA: Baseband Filter Op-Amp Bias Settings 0 = Low 1 = High
VCO Control (Register Address 0x09) VCO<1:0>: Selects 1 of 3 VCO Bands. 00 turns off VCO block completely. BS<2:0>: Selects 1 of 8 VCO Sub-Bands
*Not production tested.
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Direct-Conversion TV Tuner
DC Offset DAC (Register Address 0x0C) DC_DAC<7:0>: Value to Program to I/Q DC Offset DAC. Note that the MSB is located in the previous register. Tracking Filter ROM Address (Register Address 0x0D) TFA<3:0>: Tracking Filter ROM Address. See Table 3. Tracking Filter Write Data (Register Address 0x0E) TFD<7:0>: Tracking Filter Data for ROM Tracking Filter ROM Read Back (Read Only) (Register Address 0x10) TFR<7:0>: Tracking Filter ROM Data Read Back Status (Read Only, for Factory Use Only) (Register Address 0x11) POR: Power-On Reset* 0 = Power has not been reset since the last read. 1 = Power has been reset since the last read. Gets reset after reading back address 8'h0C.
*Not production tested.
VASA, VASE: VCO Autotuner Status* LD: PLL Lock Detector 0 = PLL unlocked 1 = PLL locked DC_HI: DC Offset Correction Detected Positive Signal Excursion in Either I or Q Channel* DC_LO: DC Offset Correction Detected Negative Signal Excursions in Either I or Q Channel* PD_OVLD: Baseband Power Detector 0 = Baseband signal below threshold 1 = Baseband signal above threshold
MAX3580
Autotuner Read Back (Read Only, for Factory Use Only) (Register Address 0x12) VCOA<1:0> VCO Tank Selected by Autotuner* BSA<1:0> Sub-Band VCO Selected by Autotuner* ADC<2:0> VCO Tank Voltage ADC*
Table 3. MAX3580 Fuse Table
BYTE 00 01 02 03 04 05 06 07 7 6 Unused VHF (200MHz) parallel cap Unused UHF low (470MHz) parallel cap UHF high (860MHz) shunt cap UHF high (860MHz) parallel cap Baseband filter UHF (8MHz) coefficient. X X X X 5 4 3 2 Bias VHF (200MHz) series cap VHF (200MHz) shunt cap UHF low (470MHz) series cap UHF low (470MHz) shunt cap UHF high (860MHz) series cap Baseband filter VHF (7MHz) coefficient. X X X RO 1 0 DESCRIPTION Bias trim VHF high series cap VHF shunt cap UHF low series cap low UHFhigh/low parallel cap UHF high series cap BB filter bandwidth Read only
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Direct-Conversion TV Tuner
To Read Back Fuses IMPORTANT NOTICE: When reading other addresses than 8'h00 (the system trim bits), it is possible that the data going to the bias cells will be disturbed due to the architecture of the fuse bank. This means the bias current could change while reading back fuse data. 1) Write 8'hXX to TFA. XX is the address of the fuse column you want to read. 2) Read 8'hXX from TFR. TFR is the Tracking Filter Read Register. 3) Repeat steps 1 and 2 for other addresses.
MAX3580
Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX3580 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time.
2-Wire Serial Interface
The MAX3580 uses a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serialclock line (SCL). The serial interface allows communication between the MAX3580 and the master at clock frequencies up to 400kHz. The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX3580 behaves as slave devices that transfer and receive data to and from the master. Pull SDA and SCL high with external pullup resistors (1k or greater) for proper bus operation. One bit is transferred during each SCL clock cycle. A minimum of nine clock cycles are required to transfer a byte in or out of the MAX3580 (8 bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy.
Slave Address The MAX3580 has a 7-bit slave address that must be sent to the device following a START condition to initiate communication. The slave address is determined by the state of the ADDR2 pin and is equal to 11000[ADDR2]0 (see Table 4). The eighth bit (R/W) following the 7-bit address determines whether a read or write operation will occur. The MAX3580 continuously awaits a START condition followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the SDA line low for one clock period; it is ready to accept or send data depending on the R/W bit (Figure 2).
START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high.
SLAVE ADDRESS
Table 4. Address Configuration
ADDRESS (WRITE/READ) C0/C1HEX C4/C5 HEX ADDR2 0 1
S
1
1
0
0
0
ADDR2
0
R/ W
ACK
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 2. MAX3580 Slave Address Byte
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Direct-Conversion TV Tuner
Write Cycle When addressed with a write command, the MAX3580 allows the master to write to a single register or to multiple successive registers. A write cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX3580 issues an ACK if the slave address byte is successfully received. The bus master must then send to the slave the address of the first register it wishes to write to. If the slave acknowledges the address, the master can then write one byte to the register at the specified address. Data is written beginning with the most significant bit. The MAX3580 again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with the MAX3580 acknowledging each successful transfer, or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition. Figure 3 illustrates an example in which Registers 0 through 2 are written with 0x0E, 0xD8, and 0xE1, respectively. Read Cycle When addressed with a read command, the MAX3580 allows the master to read back a single register or multiple successive registers. A read cycle begins with the bus master issuing a START condition followed by the 7 slave address bits and a write bit (R/W = 0). The MAX3580 issues an ACK if the slave address byte is successfully received. The bus master must then send the address of the first register it wishes to read. The slave acknowledges the address. Then a START condition is issued by the master, followed by the 7 slave address bits and a read bit (R/W = 1). The MAX3580 issues an ACK if the slave address byte is successfully received. The MAX3580 starts sending data MSB first with each SCL clock cycle. At the 9th clock cycle, the master can issue an ACK, and continue to read successive registers, or the master terminate the transmission by issuing a NACK. The read cycle does not terminate until the master issues a STOP condition. Figure 4 illustrates an example in which Registers 0 through 2 are read back.
MAX3580
START
WRITE DEVICE ADDRESS 1100000
R/ W 0
ACK
WRITE REGISTER ADDRESS 0x00
ACK
WRITE DATA TO REGISTER 0x00 0x0E
ACK
WRITE DATA TO REGISTER 0x01 0xD8
ACK
WRITE DATA TO REGISTER 0x02 0xE1
ACK STOP
Figure 3. Example: Write Registers 0 through 2 with 0x0E, 0xD8 and 0xE1, respectively.
S T A R T
DEVICE ADDRESS 11000000
R/ W 0
A C K
REGISTER ADDRESS 00000000
A C K
S T A R T
DEVICE ADDRESS 11000000
R/ W 1
A C K
REG 00 DATA xxxxxxxx
A C K
REG 01 DATA xxxxxxxx
A C K
REG 02 DATA xxxxxxxx
N A C K
S T O P
Figure 4. Example: Receive data from read registers.
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Direct-Conversion TV Tuner MAX3580
Applications Information
Band Selection
The MAX3580 is designed to be suitable for operation in the 170MHz to 230MHz VHF-III band and in the 470MHz to 878MHz UHF band.
Baseband Power Detector
Maxim recommends disabling this feature. See explanation in the Shutdown Control (Register Address 0x08) section and Table 2 (address 0x08, bit D5). For singleloop AGC control, see Figure 1.
Synthesizer Loop Filters
A second-order lowpass loop filter is used to connect the PLL to the RF local oscillator. A loop filter bandwidth of 30kHz is optimal for fractional PLL spurs and integrated LO phase noise. Refer to the EV kit data sheet for the recommended loop-filter component values.
RF Inputs
A switch selects either RFIN or RFIN2 as the input to the single-ended broadband matched LNA. This switch is programmed through the RFS bit (bit 5) of register 0x05. The LNA provides a continuous gain control range of typically 50dB before the signal is downconverted. For optimal matching above 600MHz, add a 5nH to 6nH inductor in series with a capacitor at either of the RF input. Application Note: Front End Diplexer Filter for MAX3580 is available, detailing the implementation of a UHF and VHF simple diplexer. This simple diplexer improves strong-signal-handling capabilities of the MAX3580.
Crystal-Oscillator Interface
The MAX3580 reference oscillator circuitry can be used either as a high-impedance reference input driven by an external source, or be configured as a crystal oscillator. In the latter case, the resulting frequency can be used to drive the digital demodulator chip through the buffered reference output of the MAX3580. When using an external reference oscillator, drive the XB input through an AC-coupling capacitor with amplitude of approximately 1.5V P-P, and leave XE unconnected. Note that the phase noise of the external reference needs to exceed -140dBc/Hz at offsets of 1kHz to 100kHz. When connecting directly to a crystal, see the Typical Application Circuit for the required topology. For particular capacitor values, possible changes to accommodate for different crystal frequencies, crystal load-capacitance requirements, and crystal power-dissipation requirements, refer to the EV kit data sheet.
DC-Offset Cancellation
The MAX3580 features an on-chip fast-settling, DC-offset cancellation circuitry that requires no off-chip components. Note that the offset correction circuit is not enabled when the device is powered up. To enable the offset correction circuit, program the DC-Offset Control Register to the recommended default setting. When active, the offset correction circuit creates a highpass characteristic in the signal path with a typical corner frequency of 200Hz, and the residual DC offset can be as high as 70mV.
Gain Control
The MAX3580 features two VGA circuits that can be used to achieve the optimum SNR. The two circuits can be driven independently by the baseband controller, which allows balancing the gain based on SNR measurements in the digital demodulator. If only one gain control voltage can be provided by the digital demodulator, see Figure 1. See the Baseband Power Detector section. In this operation mode, the baseband gain is set by an amplitude detector in the digital demodulator.
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Direct-Conversion TV Tuner
RF Tracking Filter
The MAX3580 utilizes two narrowband RF tracking filters, one for VHF and one for UHF. Each filter is comprised of a fixed inductor and three digitally controlled variable capacitors named series, shunt, and parallel capacitors. The integrated RF tracking filters uses an external inductor between IND1 and IND2 pins to set the filter's center frequency. The inductor value must be 68nH 2% in order to achieve the corner frequency response. The variable capacitors are factory calibrated to this particular inductor value. The value of each capacitor is also set to compensate for process variation of each individual part and to receive the desired RF channel. The process variation is factory calibrated by determining the best capacitor values for three discrete frequencies, which are stored in the on-chip ROM table. Upon power-up these values (6 bytes total) have to be read out of the MAX3580 ROM table and stored in the microprocessor local memory. When tuning the MAX3580 to a given Rx frequency, the correct capacitor value has to be calculated using the following linear formulas and written to the appropriate registers. This is in addition to programming the PLL with the desired frequency. The formulas differ for VHF and UHF bands but are the same for all three capacitor values. Since the factory calibration coefficients stored on the MAX3580 can differ for each capacitor, the calculations have to be executed for all three capacitor values separately. VHF: Capacitor = ROM_value_VHF (RX_frequency_in_MHz - 200MHz ) / 10MHz In other words, the capacitor values to be written to the MAX3580 decrease 1 count per 10MHz above 200MHz and increase accordingly below 200MHz. UHF: Capacitor = ROM_value_UHF_lo (ROM_value_UHF_lo - ROM_value_UHF_hi) x (RX_frequency_in_MHz - 470MHz ) / 390MHz This means the capacitor values stored in the UHF_lo entries of the MAX3580 ROM table are the correct values for 470MHz reception and the UHF_hi values for 860MHz reception. For any frequency in between, the capacitor values are obtained by a simple linear interpolation. Note: When tuning to frequencies above 860MHz channel center frequency, do not use the formula above, but rather keep programming the tracking filter with the coefficients obtained for 860MHz. Examples: Assuming the MAX3580 ROM table entries are CSERIES VHF = 8, CSERIES UHF_lo = 15, CSERIES UHF_hi = 3 208MHz: CSERIES = 8 - round ( ( 208-200 ) / 10 ) = 7 (floating point division, round to nearest integer after division) 8 - floor ( ( 208 - 200 + 5) / 10 ) = 7 (all calculations using signed integer values, truncate result of division) 677MHz: CSERIES = 15 - round ( (15-3) x (677 - 470) / 390 ) = 9 (floating point division, round to nearest integer after division) 15 - floor ( ( ( 15-3) x (677-470) + 195 ) / 390 ) = 9 (all calculations using signed integer values, truncate result of division)
MAX3580
Power-Supply Layout
To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at the central VCC node. The VCC traces branch out from this node, with each trace going to separate V CC pins of the MAX3580. Next to each VCC pin is a bypass capacitor with a low impedance to ground at the frequency of interest. Use at least one via per bypass capacitor for a low-inductance ground connection. The three ground pins (GND_PLL, GND_CP, GND_TUNE) must be connected to the ground plane by separate via holes and must not be directly connected to the exposed paddle.
Chip Information
PROCESS: BiCMOS
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Direct-Conversion TV Tuner MAX3580
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 32 TQFN-EP PACKAGE CODE T3255-5 DOCUMENT NO. 21-0140
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Direct-Conversion TV Tuner
Revision History
REVISION NUMBER 0 1 2 3 4 5 6 7 REVISION DATE 8/06 5/07 8/07 10/07 3/08 8/08 11/08 1/09 Initial release Various changes Various changes Various changes Updated AC Electrical Characteristics, corrected Pin Description, added Figure 1, updated Figure references, various other changes Restricted PLL N-divider range and widened I/Q output DC common mode range Added note to Programmable Registers section to avoid mistuning the VCO during a channel change Updated Note 1 to specify part tested at hot temperature only DESCRIPTION PAGES CHANGED -- 1, 4, 5, 20, 21 2, 5 3, 20, 21 1, 2, 5, 7-13, 15, 17-19 3, 5, 15 12 1-5
MAX3580
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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